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Lab #04: K-Maps solution

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ECE 380 Lab #04: K-Maps

In this lab you will use the Quartus II environment to download designs to programmable devices on the Altera
DE1 board. You will create several simple designs, using VHDL and schematic entry, which will be
downloaded to the Altera DE1 board.
Please select “Cyclone V” as the device family and “5CSEMA5F31C6” as the device in the Family & Device
Setting when creating your projects.
During the lab session, you need to do the following:
1. Get your pre-lab signed by the Lab TA.

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ECE 380 Lab #04: K-Maps

In this lab you will use the Quartus II environment to download designs to programmable devices on the Altera
DE1 board. You will create several simple designs, using VHDL and schematic entry, which will be
downloaded to the Altera DE1 board.
Please select “Cyclone V” as the device family and “5CSEMA5F31C6” as the device in the Family & Device
Setting when creating your projects.
During the lab session, you need to do the following:
1. Get your pre-lab signed by the Lab TA.
2. Use Quartus II to design the minimum SOP form of f(a,b,c,d) from the pre-lab; write VHDL. Compile
and simulate the file. Print out the .vhd and .wav files. Download the design to the Altera Cyclone® V
DE1 FPGA board. Use toggle switches SW[3 … 0] for the four inputs and LEDR[7] for the function
output. Verify the design by testing all possible input valuations and observing the output f. Fill in the
pre-lab data table column, f (min SOP), with the values that you get from the DE1 board. Receive TA’s
initials after demonstrating this part of the lab.
3. Use Quartus II’s graphics editor to design the gate diagram for the minimum SOP form of f(a,b,c,d)
from the pre-lab using only NAND gates. Compile and simulate the file. Print out the .bdf and .wav
files. Download the design to the Altera Cyclone® V DE1 board. Use toggle switches SW[3 … 0] for
the four inputs and LEDR[7] for the function output. Verify the design by testing all possible input
states from the truth table and observe the output, f. Fill in the pre-lab data table column output, f
(NAND), with the values that you observed from the DE1 board. Receive TA’s initials after
demonstrating this part of the lab.
4. Use Quartus II to design the minimum POS form of g(a,b,c,d) from the pre-lab; write VHDL. Compile
and simulate the file. Print out the vhd and wav files. Download the design to the Altera Cyclone® V
DE1 board. Use toggle switches SW[3 … 0] for the four inputs and LEDR[7] for the function output.
Verify the design by testing all possible input valuations and observing the output g. Fill in the pre-lab
data table column, g (min POS), with the values that you get from the DE1 board. Receive TA’s initials
after demonstrating this part of the lab.
5. Use Quartus II’s graphics editor to design a gate diagram for the minimum POS form of g(a,b,c,d) from
the pre-lab using only NOR gates. Compile and simulate the file. Print out the bdf and wav files.
Download the design to the Altera Cyclone® V DE1 board. Use toggle switches SW[3 … 0] for the
four inputs and LEDG[7] for the function output. Verify the design by testing all possible input
valuations and observing the output g. Fill in the data table column, g (NOR), with the values that you
get from the DE1 board. Receive TA’s initials after demonstrating this part of the lab.
6. Make sure that you have printed out all of the files and received TA’s initials.
7. Turn in the lab report one week from your lab session.
Homework #04 (100 points)
1) (60 pts) Prove the following statements using algebraic manipulation.
a) (30 pts) If ?? = ?? ⨁?? ⨁?? , please prove ?? = ?? ⨁?? ⨁?? .
b) (10 pts) 0⨁?? = ??
c) (10 pts) 1⨁?? = ??̅
d) (10 pts) x⨁??̅= 1
2) (40 pts) Write the minimized SOP form for the following 6-variable K-Map:
f = ∑ m(0,1,2,3,8, 10,16,17, 18,19, 24, 26, 32,33,34,35,40, 42, 48, 50, 56, 58)