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EEL 6764 Principles of Computer Architecture
Homework #5
1 Problems
Total points: 130
1. [80 pts] Consider the code below.
Loop: fld f0, 0(x1)
fmul.d f4, f0, f2
fsd f4, 0(x1)
fsub.d f4, f10, f14
addi x1, x1, 8
bne x1, x2, Loop // branches if x1x2
Assume the following latencies:
(a) fld/fsd: 1 cycle
(b) fsub.d: 2 cycles
(c) addi/bne: 1 cycle
(d) fmul.d: 6 cycles

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EEL 6764 Principles of Computer Architecture
Homework #5
1 Problems
Total points: 130
1. [80 pts] Consider the code below.
Loop: fld f0, 0(x1)
fmul.d f4, f0, f2
fsd f4, 0(x1)
fsub.d f4, f10, f14
addi x1, x1, 8
bne x1, x2, Loop // branches if x1x2
Assume the following latencies:
(a) fld/fsd: 1 cycle
(b) fsub.d: 2 cycles
(c) addi/bne: 1 cycle
(d) fmul.d: 6 cycles
Assume that branches are predicted as taken. Execute the above code for two iterations using
1 Tomasulo’s approach
2 Hardware-based speculation
Show the step-by-step execution using the tables in Figure 3.11 (Tomasulo) and 3.16
(HW-based speculation).
What are the numbers of cycles to finish the first two iterations using the above three approached? Count the cycles from the first instruction being issued to the last instruction that
finishes.
I recommend using Excel sheets (a template is available on Canvas) to work on the above two
problems.
2. [50 pts] Execute the code in Problem 1 using hardware-based speculation and multiple issue.
Show the execution by reusing the table shown in Figure 3.24 in the book. Assume issue
width of 2.
(a) Show the status of associated reservation stations, reorder buffer, and registers after
issuing the first two instructions in cycle 1.
2 Requirement
• All homeworks should be done and submitted individually.
• Show all steps to get full points.
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EEL 6764 Fall 2018 Homework
• Writing and drawings if necessary must clear and readable. Otherwise, substantial loss of points
may occur.
• You must submit your solutions electronically via Canvas.
• The file for your solutions must be in PDF or MS-Word DOCX format or EXcel xls.
2